The nano testing Symposium (NANOTS) provides a forum for engineers and researchers especially from Japan, to present and discuss various aspects of nano testing. The official languages of the symposium are Japanese and English. Translation service is not provided.
Topics of interest include:
- ADVANCED DESIGN METHODOLOGIES FOR NANO TESTING
- Design error diagnosis
- Design for debug and diagnosis (DFD)
- Design for manufacturing (DFM)
- Design for reliability (DFR)
- Design for testability (DFT)
- Design for yield (DFY)
- ADVANCED PROCESS TECHNIQUES FOR NANO TESTING
- Interconnect: copper/low-k reliability
- Wafer preparation
- Physical characterization of wafers
- Electrical characterization of wafers
- Surface preparation: control and monitoring of surface treatment
- Cleaning
- Process control
- Dopant diffusion
- Oxidation and gate dielectrics: metrology of dielectric films
- Optical lithography
- Photomask fabrication: photomask qualification
- Equipment reliability
- In-line metrology
- Metrology for lithography processes
- Metrology for front end processes
- Interconnect process control
- In-FAB FIB
- In-situ metrology
- Yield modeling
- Yield management
- Electrical, Physical, and Chemical Characterization
- ADVANCED NANO TESTING
- System-on-chip testing
- Memory testing
- Delay testing
- Low-power testing
- Built-in self-testing
- Software-based selftesting
- Analog and mixed-signal testing
- IDDQ testing
- Burn-in testing
- FPGA testing
- High-speed I/O testing
- RF testing
- RELIABILITY PHYSICS AND ENGINEERING
- Accelerated testing
- Time-to-failure modeling
- Time-to-failure statistics
- Failure rate
- Acceleration factor
- Time-dependent dielectric breakdown
- EFFECTS OF RADIATION ON INTEGRATED CIRCUITS
- Radiation effects on semiconductor devices
- Mitigation techniques
- ADVANCED IC-LEVEL DEBUG AND DIAGNOSIS
- Silicon debug
- Defect diagnosis
- Cause-effect analysis
- Effectcause analysis
- Scan chain diagnosis
- Logic BIST diagnosis
- Memory diagnosis and built-in self-repair
- ADVANCED PROBING TECHNOLOGIES FOR DEBUG AND DIAGNOSIS
- Die exposure technique
- Mechanical probing
- Injection-based probing
- E-beam probing
- Larser beam probing (laser voltage probing, resistance change (OBIRCH, SDL))
- Emission microscopy
- Emission-based probing
- Infrared emission microscopy (IREM)
- Picosecond imaging circuit analysis (PICA)
- Time-resolved emissions (TRE)
- Others
- ADVANCED CIRCUIT EDITING FOR DEBUG AND DIAGNOSIS
- Focused Ion Beam
- Layout-database-driven navigation system
- PHYSICAL ANALYSIS TOOL FOR FAILURE ANALYSIS
- Package analysis
- Deprocessing
- Parallel polishing
- Cross-section analysis
- Microscopy
- Transmission electron microscopy (TEM)
- Others
- CHEMICAL CHARACERIZATION FOR FAILURE ANALYSIS
- X-ray analysis (energy dispersive)
- Auger
- Secondary ion mass spectroscopy (SIMS)
- Microspot Fourier transform infrared spectroscopy
- Others
- FAILURE MECHANISMS IN NEW MATERIALS AND TRANSISTORS
- Process-related issues
- Hot carriers
- NBTI
- PBTI
- Passivation stability
- Dielectric integrity
- High-k gate oxides
- Latchup
- ESD
- Metal migration: mechanical and thermal aspects
- Low-k dielectrics and Cu interconnects
- Reliability related to nanotechnology
- ECONOMICS OF NANO TESTING
- Economic effects
- Economic models
- The learning curve
- Technological driving forces
- Factory and equipment economics
- TESTING FOR NEW DEVICES (including Devices for Biological Sci- ence, Medical Applications and Health Monitoring)
- Micro Electro Mechanical Systems (MEMS, BioMEMS)
- Sensors
- Liquid Crystal Display (LCD)
- Nano-tube
- PRAM
- RRAM
- FRAM
- Others
- ADVANCED TESTING EQUIPMENT AND SYSTEMS
- Transmission electron microscope (TEM)
- Scanning electron microscope (SEM)
- Focused ion beam (FIB)
- Scanning Probe Microscope
- Others
- CASE STUDIES OF NANO TESTING
- Electrical characterization
- Die exposure
- Package analysis
- Global failure site isolation
- Probe failure site isolation
- Defect exposure
- Physical inspection
- Chemical analysis